Scope
Identify device, wafer technology, sort insertion, test program, and applicable lot types.
Free Semiconductor & Electronics Template
Define probe setup, wafer sort execution, binning, data handling, and hold criteria
Use this template to define probe setup, wafer sort execution, binning, data handling, and hold criteria.
| Field | Details |
|---|---|
| Category | Semiconductor & Electronics |
| Owner | [Team or owner] |
| Version | [Version number] |
| Effective Date | [Date] |
| Review Cycle | [Monthly / Quarterly / Annual / Event-based] |
| Status | [Draft / In Review / Approved] |
Identify device, wafer technology, sort insertion, test program, and applicable lot types.
| Item | Details | Owner | Status |
|---|---|---|---|
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
[Add context, assumptions, exceptions, evidence links, screenshots, calculations, or reviewer comments.]
List prober, tester, load board, probe card, chuck temperature, and required calibrations.
| Item | Details | Owner | Status |
|---|---|---|---|
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
[Add context, assumptions, exceptions, evidence links, screenshots, calculations, or reviewer comments.]
Define cleaning, alignment, contact resistance, touchdown limits, and maintenance triggers.
| Item | Details | Owner | Status |
|---|---|---|---|
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
[Add context, assumptions, exceptions, evidence links, screenshots, calculations, or reviewer comments.]
Provide step-by-step lot load, wafer map verification, first wafer review, and production flow.
| Item | Details | Owner | Status |
|---|---|---|---|
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
[Add context, assumptions, exceptions, evidence links, screenshots, calculations, or reviewer comments.]
Describe pass bins, fail bins, retest bins, inkless map rules, and engineering bins.
| Item | Details | Owner | Status |
|---|---|---|---|
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
[Add context, assumptions, exceptions, evidence links, screenshots, calculations, or reviewer comments.]
Specify STDF, wafer map, MES upload, backup, and customer data package requirements.
| Item | Details | Owner | Status |
|---|---|---|---|
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
[Add context, assumptions, exceptions, evidence links, screenshots, calculations, or reviewer comments.]
List yield, continuity, probe mark, temperature, and equipment alarms requiring lot hold. Use probe and ATE terminology with auditable setup values.
| Item | Details | Owner | Status |
|---|---|---|---|
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
| [Item or requirement] | [Describe the relevant detail, evidence, or decision] | [Owner] | [Open / Complete] |
[Add context, assumptions, exceptions, evidence links, screenshots, calculations, or reviewer comments.]
Document review conclusions, approvals, unresolved items, and next review date.
| Role | Name | Date | Notes |
|---|---|---|---|
| Preparer | [Name] | [Date] | [Notes] |
| Reviewer | [Name] | [Date] | [Notes] |
| Approver | [Name] | [Date] | [Notes] |
Template Structure
Use this semiconductor & electronics template as a starting point, then customize each section to match your internal workflow, evidence, and signoff needs.
Identify device, wafer technology, sort insertion, test program, and applicable lot types.
List prober, tester, load board, probe card, chuck temperature, and required calibrations.
Define cleaning, alignment, contact resistance, touchdown limits, and maintenance triggers.
Provide step-by-step lot load, wafer map verification, first wafer review, and production flow.
Describe pass bins, fail bins, retest bins, inkless map rules, and engineering bins.
Specify STDF, wafer map, MES upload, backup, and customer data package requirements.
List yield, continuity, probe mark, temperature, and equipment alarms requiring lot hold. Use probe and ATE terminology with auditable setup values.
Write a wafer sort procedure. Structure with these Markdown sections:
Identify device, wafer technology, sort insertion, test program, and applicable lot types.
List prober, tester, load board, probe card, chuck temperature, and required calibrations.
Define cleaning, alignment, contact resistance, touchdown limits, and maintenance triggers.
Provide step-by-step lot load, wafer map verification, first wafer review, and production flow.
Describe pass bins, fail bins, retest bins, inkless map rules, and engineering bins.
Specify STDF, wafer map, MES upload, backup, and customer data package requirements.
List yield, continuity, probe mark, temperature, and equipment alarms requiring lot hold.
Use probe and ATE terminology with auditable setup values.
Tester: V93000
Prober: P12 with 25 C chuck
Probe Card: PC-RS21-04, max 80k touchdowns
Clean after every wafer or when contact resistance exceeds 1.5 ohm on any power pin.
Hold lot if continuity failures exceed 2 percent or site-to-site yield delta exceeds 5 percent.
Record a walkthrough, training session, or process demonstration. Docsie AI turns it into structured documentation using this template as the starting framework.
Use the template manually, or let Docsie generate the first draft from source footage.
Track die attach, wire bond, mold, singulation, inspection, and release steps for IC assembly
Define device burn-in loading, stress conditions, monitoring, unload, and disposition
Define gowning, behavior, and contamination controls for [cleanroom area]
Create a concise semiconductor device datasheet with ratings, electrical characteristics, timing, and package data
Define electrostatic discharge controls for [electronics line/lab/fab area]
Control semiconductor or electronics product, process, test, material, or documentation changes
Template FAQ
Common questions about using and generating a wafer Sort Procedure.
Q: What is a wafer Sort Procedure?
A: A wafer Sort Procedure is a structured document for define probe setup, wafer sort execution, binning, data handling, and hold criteria.
Q: Can I download this wafer Sort Procedure as Word or PDF?
A: Yes. This page includes free downloads in DOCX, PDF, and Markdown formats so you can edit, share, or import the template into your documentation system.
Q: Can Docsie generate this from a video?
A: Yes. Upload a process walkthrough, training recording, or screen capture to Docsie, then use this template structure to generate a first draft automatically.